The base board firmware
This is a description of what the firmware of the SuperMuSR ADC120 (DAQ1x1) base board does once it is running on the instrument: what it shows, what it monitors, what the DAQ can ask of it and how it is updated. For how to compile it, see README.md.
The base board is the hub of the instrument. The four DAQ boards (A to D) plug into it, and it is the base that distributes the clock, the sync and the T0 to them, routes the sixteen front-panel LEMO connectors, powers and reads the staves, and carries the OLED display and the three buttons on the front panel. Inside its Kintex-7 FPGA there is a MicroBlaze processor, and the firmware described here is the application that runs on it.
At a glance
| What it runs on | MicroBlaze soft processor inside the base board FPGA (xc7k160t) |
| What it drives | 128x64 OLED display (SSD1306, I2C), three front-panel buttons |
| What it reads | the signal router and the base controller in the FPGA, the shared memory the DAQ writes, five temperature sensors over I2C |
| What it writes | the measured temperatures, back into the shared memory for the DAQ |
| What it can do on request | show the upgrade screen, erase / program / read back the base firmware in the SPI flash, reset the IP address of all DAQ boards |
| Display refresh | about twice a second (every two seconds while a firmware update is running) |
The firmware never takes part in data acquisition: it is the monitoring, display and maintenance processor of the board. Acquisition runs in the FPGA fabric and on the DAQ boards.
What happens at power up
The FPGA always configures itself from address 0 of the SPI flash, which holds the bootloader image. The first thing the application does is decide whether to stay there or hand over to the firmware image:
- it reads the configuration status register of the FPGA through the HWICAP
- it reads the three front-panel buttons
- then:
| Condition | What happens |
|---|---|
| the centre button is held down | the board stays in bootloader mode, and the display says so |
| the previous configuration attempt fell back | the board stays in bootloader mode |
| the board is already running the firmware image | it continues into normal operation |
| otherwise | it writes 0x800000 into the warm boot address register and triggers IPROG, and the FPGA reconfigures itself from the firmware image |
So, in normal operation, the board configures itself twice at every power up: once from the bootloader, once from the firmware. The whole sequence takes well under a second and is not visible from the outside, except that the display starts in the firmware image.
Bootloader mode is the recovery state of the board. It is reached on purpose, by holding the centre button while powering up, and by itself whenever the firmware image is missing or half written. The display shows:
BOOTLOADER
This device entered in bootloader mode.
The base can be reprogrammed from DAQ.In this state nothing is monitored and no screen can be browsed: the board waits for the DAQ to rewrite the firmware image. This is why the bootloader is never updated in the field - as long as it is intact, a board can always be recovered.
The front panel display
Three buttons, and they mean the same thing everywhere:
| Button | What it does |
|---|---|
| right | next screen |
| left | previous screen, or back to the top of the group |
| centre | cycles the pages of the current screen, where there are several (DAQ 1-4, LEMO 1-8 / 9-16, stave 1-4) |
Buttons are debounced over about an eighth of a second, and one press is one action: holding a button down does not repeat it.
The screens, in order
Starting from the home screen and pressing right:
| Screen | What it shows |
|---|---|
| Home | the Nuclear Instruments logo and the digitizer ID of the instrument |
| DAQ status | per DAQ board, where it is in its own startup sequence: Booting, FW UP, App Start, ADC 1...4 Cfg, Stave Cfg, HV Cfg, Kafka Cfg, Zmq Cfg, Ready, Running, Error. A board whose link to the base is down shows --- |
| TRG | the trigger rate of each DAQ board |
| IP | the IP address of each DAQ board |
| LAN | per DAQ board, whether the link is up and whether the address came from DHCP or is static |
| VER | the firmware version of each DAQ board |
| LEMO direction (two pages) | for each of the sixteen LEMO connectors, whether it is an input or an output |
| LEMO rate (two pages) | the frequency measured on each LEMO connector |
| LEMO function (two pages) | what each LEMO output carries (T0, TRG, CLK, BUSY, SYNC, a DAQ line such as D1_0, a fixed level, ...) |
| T0 | where the T0 comes from and the rate measured on it |
| CLK | the clock source (INT, EXT, an RJ45 or LVDS line) and the frequency measured on it |
| SYNC | the sync source and its rate |
| DAQ 1-4 function (one page per DAQ) | what each of the eight sync lines towards that DAQ board carries |
| Stave info | whether the staves are powered, and the firmware version of each of the four |
| SiPM T, stave 1-4 | the temperature of the eight SiPMs of each stave |
| Heater, stave 1-4 | the heater voltage of the eight positions of each stave |
| HV | the four high voltage channels |
| DAQ temp | the temperature of each DAQ board, --- where no sensor answers |
| Base info | the base board firmware version, the serial number of the instrument, the temperature of the base |
Two screens appear by themselves, whatever was being shown:
BASE FW UPGRADE, while the DAQ is rewriting the base firmware (see below)EMERGENCY- All DAQ have been disabled due over-temperature. The firmware raises it as soon as the over-temperature flag of the temperature monitor is set; pressing any button acknowledges it, and it comes back if the condition clears and sets again
Resetting the IP addresses of the DAQ boards
This is the one setting that can be changed from the panel, and it is deliberately awkward to
reach by accident: from the IP screen, press centre to get the IP RESET screen, then
press centre five times. The firmware then asks all four DAQ boards to go back to their
default address as a static address, and confirms:
IP of all DAQ has been restored to default values and set as static.The counter on the screen shows how many of the five presses have been registered; leaving the screen at any point cancels it.
What the firmware monitors, and where it comes from
Everything on the screens is read fresh at every refresh. There is no history and nothing is stored: the display is a window on the current state.
| Quantity | Read from |
|---|---|
| LEMO direction, output function, measured rate | the signal router in the FPGA |
| clock, sync, T0 and SP source and measured rate | the signal router in the FPGA |
| sync lines towards each DAQ board | the signal router in the FPGA |
| stave power, base board version, DAQ link status | the base controller in the FPGA |
| DAQ state, IP, DHCP and link flags, version, trigger rate | the shared memory, written by the DAQ boards |
| SiPM temperatures and heater voltages of the staves, HV, serial number, digitizer ID | the shared memory |
| temperature of the four DAQ boards and of the base | an I2C temperature monitor on the board, read directly by this firmware |
The temperatures are the only quantity this firmware measures itself, and it publishes them back into the shared memory so that the DAQ software can read them too.
What the DAQ can ask of the base
The DAQ talks to this firmware through a small command window in the shared memory: it writes a command, the firmware executes it and writes back a status (not executed, in progress, success, error). The command register is cleared as soon as it is read, so each command is executed once.
| Command | What the firmware does |
|---|---|
| show the upgrade screen | switches the display to BASE FW UPGRADE |
| erase | erases the flash from 0x800000 for the size of the image being sent, rounded up to whole 64 KB sectors |
| program a page | writes the 256 byte page the DAQ left in the shared memory, at the offset it asks for |
| read back a page | reads 256 bytes from the flash and leaves them in the shared memory for the DAQ to compare |
Updating the base firmware
The base firmware is updated from the DAQ, over the shared memory, while the board keeps running from the bootloader or from the current firmware. The DAQ software drives the whole sequence; what this firmware contributes is the flash access and the progress on the display:
| Display | What is happening |
|---|---|
ERASE FLASH | the flash sectors of the firmware image are being erased |
PROGRAMMING: <offset> | pages are being written, the number is the offset reached |
VERIFY: <offset> | pages are being read back and compared |
COMPLETED | the image is complete |
The new image takes effect at the next power cycle, because it is the FPGA that has to be reconfigured from it. Only the firmware image is ever written this way: the bootloader at address 0 is left alone, which is what guarantees that an interrupted update can be retried rather than leaving a dead board.
If an update is interrupted - power lost halfway, a corrupted file - the FPGA fails to configure from the firmware image, falls back, and the board comes up in bootloader mode ready for another attempt. Nothing has to be done on the bench to recover it.
Installing the two images on a new board
The package daq1x1-base-fpga
publishes the two images separately:
| Artifact | File | Where it goes in the SPI flash |
|---|---|---|
daq1x1-base-fpga-bootloader | base-bootloader.bin | address 0 |
daq1x1-base-fpga-firmware | base-firmware.bin | address 0x800000 |
A board that has never been programmed needs both, written with a JTAG programmer. After that, only the firmware image is ever replaced, and it can be replaced from the DAQ.
The two files are built from the same design and differ only in which half of the flash they are meant for; writing them the other way round leaves a board that configures but never reaches normal operation.
Known limitations
- HV screen. The current of the four channels always reads
0uA, and the value shown as the voltage is in fact the current register: the firmware overwrites the voltage with it while refreshing. The HV values reported by the DAQ software are the ones to trust - No history. Temperatures, rates and states are shown live only; nothing is logged on the board. Trends have to be collected by the DAQ software
- Bootloader mode is blind. While in bootloader mode the board monitors nothing and shows no screen other than its own: this is by design, but it means a board held in bootloader mode looks the same as a board with a broken firmware image
Troubleshooting
| What you see | What it means |
|---|---|
the display stays on BOOTLOADER | the centre button was held at power up, or the firmware image is missing or corrupted. Power cycle without touching the buttons; if it comes back, reprogram the firmware image from the DAQ |
a DAQ board shows --- everywhere | its link to the base is down: the board is not powered, not seated, or still booting |
a DAQ board stays in a configuration state (ADC 2 Cfg, HV Cfg, ...) | that step of its own startup is not completing - the problem is on that board, not on the base |
DAQ temp shows --- for a board | no answer from that temperature sensor |
EMERGENCY appears | the temperature monitor has disabled the DAQ boards. Check airflow and ambient temperature; acknowledging the screen does not re-enable them |
| the display is blank but the instrument works | the OLED or its I2C bus has a problem; acquisition is unaffected, as the display is only monitored by this firmware |
| the buttons do nothing | the board is either in bootloader mode or showing the upgrade screen, where navigation is suspended |
DAQ1x1 Base FPGA
FPGA design of the base board of the SuperMuSR ADC120 (v2 hardware): a Kintex-7
xc7k160tfbg676-1 with a MicroBlaze inside that drives the OLED display, the I²C sensors and
the SPI flash of the board. Every build produces one configuration image with the MicroBlaze
application already in it, and the package carries the two the board needs: the bootloader,
which the FPGA loads at power up, and the firmware, which the bootloader reconfigures the
FPGA with. Keeping both in one release is what makes a board reprogrammable in the field: the
bootloader stays, the firmware is what gets replaced.
Built with Vivado/Vitis 2020.2 in two steps — the MicroBlaze application, compiled against the
platform generated from top_base.xsa, then the implementation that embeds it in the bitstream.
License:
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